Most current-generation dynamic random access memories (DRAMs) utilize CMOS technology. Although the term "CMOS" is an acronym for (C)omplementary (M)etal (O)xide (S)emiconductor, the term CMOS is now loosely applied to any integrated circuit in which both n-channel and p-channel field-effect transistors (FETs) are used in a complementary fashion. Although CMOS integrated circuit devices are often referred to as semiconductor devices, such devices are fabricated from various materials which are either electrically conductive, electrically nonconductive, or electrically semiconductive.
Silicon is the most commonly used semiconductor material and is used in either single-crystal or polycrystalline form. Polycrystalline silicon is referred to hereinafter as "polysilicon" or simply as "poly". Silicon can be made conductive by doping it (introducing an impurity into the silicon crystal structure) with either an element having at least one less valence electron than silicon, such as boron, or with an element having at least one more valence electron than silicon, such as phosphorus or arsenic. In the case of boron doping, electron "holes" become the charge carders and the doped silicon is referred to as positive or p-type silicon. In the case of phosphorus or arsenic doping, the additional electrons become the charge carders and the doped silicon is referred to as negative or n-type silicon. As common in the art, a plus or a minus superscript on an "n" or "p" indicates heavy or light doping, respectively. If a mixture of dopants having opposite conductivity types is used, counterdoping will result, and the conductivity type of the most abundant impurity will prevail.
Conventional CMOS processing formed n-channel (NMOS) and p-channel (PMOS) devices in parallel using many masking steps and requiring excessive processing, thereby increasing costs and reducing device reliability. However, recent developments in split-polysilicon processing provide advantages such as fewer masking steps, reduced processing costs, and improved device reliability. A split-polysilicon process is one where the NMOS transistor gate is patterned in a separate photo lithograph and etch step from the PMOS transistor gate in the CMOS process flow.
Although split-polysilicon processing has provided advantages over conventional CMOS methods, there continues to be room for improvement in split-polysilicon processing techniques because of the consistently high consumer demand for improved and cheaper semiconductor devices. Accordingly, objects of the present invention are to provide an improved split-polysilicon process for forming CMOS devices.